Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes

This paper presents an asynchronous scheduling algorithm for high-throughput stochastic low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware and can be implemented using binary or multiple-valued logic gates. Using asynchronous control, it also eliminates a global clock signal and therefore eases the worst-case timing restrictions. A timing model of asynchronous-computation behaviours under a 90nm CMOS technology is used to demonstrate that the proposed algorithm with an optimized computation delay properly decodes a regular (1024, 512) LDPC code without the "lock-up" problem that potentially stops decoding before convergence and hence causes loss in coding gain. Based on our models, the proposed scheme achieves up to 7.37x improvement in decoding throughput with comparable BER performance in comparison with performance results of a conventional synchronous stochastic decoder.