A self-timed real-time sorting network

Author

Yun, Kenneth Y. ; Chakraborty, Supratik ; James, Kevin W. ; Fairlie-Cuninghame, Robert ; Cruz, Rene L.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA

fYear

1998

fDate

5-7 Oct 1998

Firstpage

427

Lastpage

434

Abstract

High speed networks are expected to carry traffic classes with diverse Quality of Service (QoS) guarantees. For efficient utilization of resources, sophisticated scheduling protocols are needed; however; these must be implemented without sacrificing the maximum possible bandwidth. This paper presents the architecture and implementation of a self-timed real-time sorting network to be used in packet switches that support a diverse mix of traffic. The sorting network receives packets with appropriately assigned priorities, and schedules the packets for departure in a highest-priority-first manner. The circuit implementation uses zero-overhead, self-timed, self-precharging domino logic and timed-roadblock techniques to minimize the circuit latency. Experimental chips being built using the techniques described in this paper support 10 Gb/s links with ATM size packets

Keywords

packet switching; protocols; sorting; ATM size packets; circuit implementation; diverse quality of service guarantees; domino logic; packet switches; scheduling protocols; self-timed real-time sorting network; timed-roadblock techniques; traffic classes; Bandwidth; Delay; High-speed networks; Logic circuits; Packet switching; Protocols; Quality of service; Sorting; Switches; Telecommunication traffic;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-9099-2

Type

conf

DOI

10.1109/ICCD.1998.727085

Filename

727085