• DocumentCode
    2297913
  • Title

    Hierarchical pipelining for behaviors, loops, and operations

  • Author

    Bakshi, Smita ; Gajski, Daniel

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
  • fYear
    1998
  • fDate
    5-7 Oct 1998
  • Firstpage
    450
  • Lastpage
    455
  • Abstract
    Behavioral specifications of DSP systems generally contain a number of nested loops. In order to obtain high date rates for such systems, it is necessary to pipeline them across their tasks, loops, and operations. This paper presents an algorithm for pipelining a given throughput-constrained system at these three different levels of granularity, while at the same time, scheduling the operations within the loop bodies and selecting components for them. Results demonstrate the feasibility and quality of our approach, and also indicate that it may be used for synthesis or estimation purposes in system-level design
  • Keywords
    circuit layout CAD; data flow graphs; DSP systems; behavioral specifications; behaviors; granularity; hierarchical pipelining; loops; nested loops; operations; system-level design; throughput-constrained system; Computer science; Delay; Digital signal processing; Digital systems; Pipeline processing; Scheduling algorithm; Signal processing algorithms; Signal synthesis; System-level design; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-8186-9099-2
  • Type

    conf

  • DOI
    10.1109/ICCD.1998.727089
  • Filename
    727089