Static race verification for networks with reconvergent clocks

We introduce a new method for pruning combinational paths in a static timing verifier. Our method is fast and robust, even for networks with min-max delays on reconvergent clock trees. We will show that current techniques for static timing verification are either not robust or not efficient for such networks. We will also show that these networks are becoming increasingly important with newer low-power, high-speed integrated circuits. We propose a new pruning strategy for such networks which is both correct and efficient