A Fault-Tolerant Area-Efficient Current-Mode ADC for Multiple-Valued Neural Networks

Author

Saffar, Farinoush ; Mirhassani, Mitra ; Ahmadi, Majid

Author_Institution

Electr. & Comput. Eng. Dept., Univ. of Windsor, Windsor, ON, Canada

fYear

2012

fDate

14-16 May 2012

Firstpage

250

Lastpage

255

Abstract

In this paper a new expandable current-mode Analog to Digital Conversion method is proposed for multiple-valued neural networks. The proposed method employs a semi-parallel architecture of current comparators to reduce the conversion time. A feedback path is used to regulate the outputs of the comparators and prevent the possible errors in the reference currents to propagate to the outputs. The circuits for a sample 4-bit conversion are designed and simulated in CMOS 180nm technology from TSMC with a 1.8v power supply.

Keywords

CMOS integrated circuits; analogue-digital conversion; current comparators; fault tolerance; multivalued logic circuits; neural nets; ADC; CMOS; TSMC; analog to digital conversion; current comparator; fault tolerant; feedback path; multivalued neural network; sample 4-bit conversion; semiparallel architecture; size 180 nm; voltage 1.8 V; Delay; Fault tolerance; Fault tolerant systems; Logic gates; Neural networks; Regulators; Transistors; Analog to Digital Converter; Current-Mode; Multiple-Valued Neural Network;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic (ISMVL), 2012 42nd IEEE International Symposium on

Conference_Location

Victoria, BC

ISSN

0195-623X

Print_ISBN

978-1-4673-0908-0

Type

conf

DOI

10.1109/ISMVL.2012.31

Filename

6214817