An SoC with automatic bias optimization of an RF oscillator

We present a novel scheme for optimizing an RF oscillator´s current to ensure MOS device reliability and improve performance of a wireless SoC. The proposed method calculates the variance of the digitized phase error samples by a time-to-digital converter (TDC) in an all-digital phase-locked loop (ADPLL) to estimate oscillator noise as a function of the current setting. The entire calibration mechanism is autonomous and fully internal to the SoC and is aided by the available on-chip processor associated with the radio modem. This concept is incorporated in a commercial single-chip radio SoC fabricated in 90-nm CMOS for GSM/EDGE mobile handsets, where it ensures compliance with the targeted phase-noise performance across temperature and process variations.