High speed and memory efficient VLSI architecture of 2D 5/3 DWT using interlaced scan algorithm for JPEG2000

Author

Wen-song Liu ; Jing Gu ; Hai-tao Zhai ; Fan Zhang

Author_Institution

28th Res. Inst., China Electron. Technol. Group Corp., Nanjing, China

fYear

2012

fDate

29-31 Dec. 2012

Firstpage

180

Lastpage

184

Abstract

2D 5/3 discrete wavelet transform (DWT) involving complexed computation and huge memory consumption is one of the key components for the lossless mode of JPEG2000. The interlaced scan algorithm (ISA) of 2D 5/3 DWT is proposed, which scans a N×N image data in the order of interlaced lines and columns to compute, and only N-depth transpose memory is needed. Compared with the best conventional methods, the transpose memory is reduced by 50%. Based on the proposed memory efficient algorithm, the high speed VLSI architecture is designed with the parallel and pipeline schemes used. The synthesis results using the library TSMC 0.18μm show that the frequency can reach 333MHz.

Keywords

VLSI; discrete wavelet transforms; image coding; integrated circuit design; parallel architectures; pipeline processing; storage management; 2D 5/3 DWT; ISA; JPEG2000; N-depth transpose memory; complexed computation; discrete wavelet transform; high speed memory efficient VLSI architecture; image data; interlaced columns; interlaced lines; interlaced scan algorithm; library TSMC; memory consumption; memory efficient algorithm; parallel schemes; pipeline schemes; transpose memory; Discrete Wavelet Transform; Interlaced Scan Algorithm; JPEG2000; Transpose Memory; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Network Technology (ICCSNT), 2012 2nd International Conference on

Conference_Location

Changchun

Print_ISBN

978-1-4673-2963-7

Type

conf

DOI

10.1109/ICCSNT.2012.6525916

Filename

6525916