• DocumentCode
    2298180
  • Title

    Profiling for input predictable threads

  • Author

    Codrescu, Lucian ; Wills, D. Scott

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    1998
  • fDate
    5-7 Oct 1998
  • Firstpage
    558
  • Lastpage
    565
  • Abstract
    Thread level speculative execution, together with value prediction to break data dependencies between threads, may enable efficient single program execution on a closely coupled chip multiprocessor. This paper describes a method to partition sequential programs such that a minimum number of hard-to-predict data dependencies cross thread boundaries. SPEC95 binaries are partitioned and then executed on an idealized simulator in order to study the limits of this technique. Value prediction is shown to be crucial to exposing thread level parallelism (TLP). Simple value predictors promise modest to large gains if thread boundaries are properly identified. Concurrent execution of fully data independent threads on 8 processors gives a geometric mean speedup of 2.4 for the benchmarks studied
  • Keywords
    computer architecture; microprocessor chips; performance evaluation; closely coupled chip multiprocessor; data dependencies; fully data independent threads; geometric mean speedup; idealized simulator; input predictable threads; profiling; single program execution; thread level parallelism; value prediction; Computational modeling; Hardware; Identity-based encryption; Microarchitecture; Operating systems; Parallel processing; Performance gain; VLIW; Wires; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-8186-9099-2
  • Type

    conf

  • DOI
    10.1109/ICCD.1998.727109
  • Filename
    727109