Title :
A 10ps 500MHz time-to-digital converter in 0.18μm CMOS technology for ADC
Author :
Yazhou Li ; Qingsheng Hu
Author_Institution :
Inst. of RF-&OE-lCs, Southeast Univ., Nanjing, China
Abstract :
This paper presents a 10ps 500MHz time-to-digital converter (TDC) in 0.18μm CMOS technology. Based on the Vernier delay line structure, the TDC can achieve high resolution, high speed and a dynamic range of 0 ~ 640ps. To increase the accuracy, the delay line cells are designed using full-custom design method. Additional, the delay cells are divided into 6 groups along the long horizontal direction of layout to have a good tradeoff between the accuracy and complexity. Another two blocks pipelined readout circuit and encoder are designed in semi-custom method to reduce the design complexity. A built-in test block generating different time interval is also embedded in the TDC to facilitate the measurement. This TDC has been tapped out and the total area including I/O pads is 1252μm×705μm. Post simulation results indicate that the TDC can work correctly at 500MHz and have a resolution of 10ps.
Keywords :
CMOS integrated circuits; UHF integrated circuits; circuit simulation; delay lines; encoding; integrated circuit design; integrated circuit layout; integrated circuit testing; readout electronics; time-digital conversion; ADC; CMOS technology; I-O pad; TDC; Vernier delay line cell structure; built-in test block; circuit layout; circuit simulation; design complexity reduction; encoder design; frequency 500 MHz; full-custom design method; pipelined readout circuit design; semicustom method; size 0.18 mum; time 0 ps to 640 ps; time-to-digital converter; analog-digital converter; built-in test; encoder; pipelined readout; time-to-digital converter; vernier delay line;
Conference_Titel :
Computer Science and Network Technology (ICCSNT), 2012 2nd International Conference on
Conference_Location :
Changchun
Print_ISBN :
978-1-4673-2963-7
DOI :
10.1109/ICCSNT.2012.6525928
