A 500 MHz, one volt, 16 by 16 bit multiplier for DSP cores

Digital signal processing (DSP) chips are of prime interest in the rapidly growing wireless communications market. Although the demand for higher performance continues to escalate, power consumption is also a concern. The most direct way to lower the power is to lower the supply voltage. Scaling technologies into the sub-micron domain has also led to the scaling of the supply voltage due to excessively high electric fields. Lowering the supply voltage by itself lowers power consumption but the performance degrades drastically. In order to improve performance while lowering the supply voltage it is necessary to scale the threshold voltage along with the supply voltage. This paper focuses on a 16 by 16 array multiplier that operates with a one volt power supply at a clock frequency of 500 MHz. The multiplier is implemented in dual rail domino logic using a 0.25 μm multi-threshold CMOS process and has four cycles of latency