DocumentCode :
2298595
Title :
Fully integrated dual-band power amplifiers with on-chip baluns in 65nm CMOS for an 802.11n MIMO WLAN SoC
Author :
Afsahi, Ali ; Behzad, Arya ; Magoon, Vikram ; Larson, Lawrence E.
Author_Institution :
Broadcom Corp., San Diego, CA, USA
fYear :
2009
fDate :
7-9 June 2009
Firstpage :
365
Lastpage :
368
Abstract :
Fully integrated dual-band power amplifiers with on-chip baluns for 802.11 n MIMO WLAN applications are presented. With a 3.3 v supply, the PAs produce a saturated output power of 28.3 dBm and 26.7 dBm with peak drain efficiency of 35.3% and 25.3% for the 2.4 GHz and 5 GHz bands, respectively. By utilizing multiple fully self-contained linearization algorithms, an EVM of -25 dB is achieved at 22.4 dBm for the 2.4 GHz band and 20.5dBm for the 5 GHz band while transmitting 54 Mbs OFDM. The chip is fabricated in standard 65 nm CMOS and the PAs occupy 0.31 mm2 (2.4 G) and 0.27 mm2 (5G) area.
Keywords :
CMOS integrated circuits; MIMO communication; MMIC power amplifiers; OFDM modulation; system-on-chip; wireless LAN; 802.1 In MIMO WLAN SoC; CMOS; OFDM; bandwidth 2.4 GHz; bandwidth 5 GHz; fully integrated dual-band power amplifiers; multiple fully self-contained linearization algorithms; on-chip baluns; peak drain efficiency; saturated output power; size 65 nm; voltage 3.3 V; CMOS process; Costs; Dual band; Impedance matching; Linearity; MIMO; OFDM modulation; Packaging; Power amplifiers; Wireless LAN; 802.11n; CMOS; Linearization; MIMO; OFDM; Power Amplifier; WLAN;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE
Conference_Location :
Boston, MA
ISSN :
1529-2517
Print_ISBN :
978-1-4244-3377-3
Electronic_ISBN :
1529-2517
Type :
conf
DOI :
10.1109/RFIC.2009.5135559
Filename :
5135559
Link To Document :
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