DocumentCode
2299049
Title
Low-power 4-2 and 5-2 compressors
Author
Prasad, Karuna ; Parhi, Keshab K.
Author_Institution
Morphics Technol. Inc., Campbell, CA, USA
Volume
1
fYear
2001
fDate
4-7 Nov. 2001
Firstpage
129
Abstract
This paper explores various low power higher order compressors such as 4-2 and 5-2 compressor units. These compressors are building blocks for binary multipliers. Various circuit architectures for 4-2 compressors are compared with respect to their delay and power consumption. The different circuits are simulated using HSPICE. A new circuit for a 5-2 compressor is then presented which is 12% faster and consumes 37% less power.
Keywords
SPICE; circuit simulation; digital arithmetic; digital circuits; digital signal processing chips; 4-2 compressor units; 5-2 compressor units; HSPICE; binary multipliers; circuit architectures; circuit simulation; delay; higher order compressors; low power compressors; power consumption; Adders; CMOS logic circuits; Compressors; Delay; Digital arithmetic; Digital signal processing; Energy consumption; Integrated circuit interconnections; Microprocessors; Power dissipation;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-7147-X
Type
conf
DOI
10.1109/ACSSC.2001.986892
Filename
986892
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