Title :
Fault Tolerant Computing Paradigm for Random Molecular Phenomena: Hopfield Gates and Logic Networks
Author :
Tran, A.H. ; Yanushkevich, S.N. ; Lyshevski, S.E. ; Shmerko, V.P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Calgary, Calgary, AB, Canada
Abstract :
This paper contributes to robust fault-tolerant computing for expected nano-centric processing hardware. We developed (a) techniques for fault tolerant logic network design given a library of AND, OR, NAND, and NOR Hop field gates, and (b) report experimental results on fault tolerant properties of designed networks. In particular, several hundred iterations are required to achieve correct outputs in a five-input single-output networks in the presence of 40% noise.
Keywords :
fault tolerant computing; logic design; logic gates; molecular electronics; Hopfield gates; fault tolerant computing; fault tolerant logic network design; logic network; nanocentric processing hardware; random molecular phenomena; Fault tolerance; Fault tolerant systems; Libraries; Logic gates; Merging; Neurons; Noise; Hopfield network; fault-tolerance; logic network; noise model;
Conference_Titel :
Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on
Conference_Location :
Tuusula
Print_ISBN :
978-1-4577-0112-2
Electronic_ISBN :
0195-623X
DOI :
10.1109/ISMVL.2011.21
