• DocumentCode
    2299411
  • Title

    A new framework for integrated global local scheduling

  • Author

    Mantripragada, Srinivas ; Jain, Suneel ; Dehnert, Jim

  • Author_Institution
    High Performance Programming Environ. Group, Silicon Graphics Comput. Syst., Mountain View, CA, USA
  • fYear
    1998
  • fDate
    12-18 Oct 1998
  • Firstpage
    167
  • Lastpage
    174
  • Abstract
    Global Instruction Schedulers can be classified as either structure or profile driven. Structure driven approaches attempt to find instruction level parallelism by redistributing instructions along all possible execution paths. When resources are limited, poor choices may penalize the frequently executed paths. By contrast, profile driven approaches use feedback information to identify frequently executed (hot) regions, and attempt to improve their performance. This may be at the expense of less frequently executed (cold) regions, for instance by inserting fixup code. The overall performance improves if the frequency information is accurate and there is a dominant trace in the program. If either of these conditions does not hold, performance may degrade. We present a novel algorithm that attempts to combine the individual merits of the above two approaches while avoiding some of their drawbacks. We have also incorporated several techniques which improve the global scheduling performance on out-of-order (OOO) processors. Our algorithm is integrated with a parametric resource model and can be applied both before and after register allocation. It has been implemented in the SGI MIPSpro compiler, and the results have been evaluated on the MIPS R8000 and R10000 processors
  • Keywords
    parallel architectures; processor scheduling; SGI MIPSpro compiler; global local scheduling; global scheduling; instruction level parallelism; parametric resource model; performance; register allocation; Computer graphics; Data mining; Degradation; Electronic switching systems; High performance computing; Out of order; Processor scheduling; Programming environments; Registers; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Architectures and Compilation Techniques, 1998. Proceedings. 1998 International Conference on
  • Conference_Location
    Paris
  • ISSN
    1089-795X
  • Print_ISBN
    0-8186-8591-3
  • Type

    conf

  • DOI
    10.1109/PACT.1998.727189
  • Filename
    727189