DocumentCode
2299436
Title
Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network
Author
Sultana, Sayeeda ; Radecka, Katarzyna
Author_Institution
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, QC, Canada
fYear
2011
fDate
23-25 May 2011
Firstpage
147
Lastpage
152
Abstract
We present an efficient way to realize reversible circuits directly from irreversible gate level descriptions, avoiding a search for reversible specifications of the original functions. In our scheme Toffoli-based implementation of classical gates can be used in topological order mapping. The method is then extended by introducing the notion of super cells, to reduce the number of extraneous bits and gate count. Our experimental results illustrate the impact of super cells on the size of the resulting reversible circuit. The results are better than previously proposed methods and BDD-based reversible synthesis approach.
Keywords
binary decision diagrams; logic circuits; logic design; logic gates; BDD-based reversible synthesis approach; Rev-map; Toffoli-based implementation; classical gates; classical irreversible network; direct gateway; gate count; irreversible gate level descriptions; reversible circuits; reversible specifications; super cells; topological order mapping; Adders; Boolean functions; Data structures; Inverters; Libraries; Logic gates; Optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on
Conference_Location
Tuusula
ISSN
0195-623X
Print_ISBN
978-1-4577-0112-2
Electronic_ISBN
0195-623X
Type
conf
DOI
10.1109/ISMVL.2011.38
Filename
5954224
Link To Document