• DocumentCode
    2299640
  • Title

    Mitigating the cache data pollution by using branch path tracking

  • Author

    Liu Song-He ; Song Huan-Sheng ; Qi Shu-Min ; Zhang Jun

  • Author_Institution
    Dept. of Inf. Eng., Chang An Univ., Xi´an, China
  • fYear
    2012
  • fDate
    29-31 Dec. 2012
  • Firstpage
    574
  • Lastpage
    578
  • Abstract
    “Memory Wall” is one of the most important problems which must be solved for designing high performance processors. Efficient and intelligent cache system is key component of processor´s memory system. We notice that cache pollution caused by the speculative execution of memory accessing instructions in predictive path may affect the cache and processor performance seriously. Based on the analyses of the impacts of speculative execution and cache data pollution to processor performance, this paper proposes a cache pollution control technique by using branch paths tracking, which is called Contra. Firstly, we construct a branch paths tracking table to follow the cache data written by memory accessing instructions in speculative branch paths. Then, processing of storage, accessing and replacement to these data are particularly controlled in order to mitigate influence of data pollution to cache system and processor performance. Simulation result indicates that, Contra technique eliminates cache pollution and upgrades performance effectively. Relative to the baseline architecture, D-Cache hit rate increases from 0.03% to 6.69%, average 1.80%. Improvement of IPC ranges from 0.01% to 6.60%, average 2.56%.
  • Keywords
    cache storage; data handling; parallel architectures; predictive control; Contra technique; D-cache hit rate; IPC ranges; branch path tracking; branch path tracking table; branch paths tracking; cache data pollution; cache data pollution mitigation; cache pollution control technique; cache system; data pollution; data replacement; high performance processors; intelligent cache system; memory accessing instructions; memory wall; predictive path; processor memory system; processor performance; speculative execution impacts; speculative memory execution; Branch Prediction; Cache; Pollution; Speculative Accessing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Science and Network Technology (ICCSNT), 2012 2nd International Conference on
  • Conference_Location
    Changchun
  • Print_ISBN
    978-1-4673-2963-7
  • Type

    conf

  • DOI
    10.1109/ICCSNT.2012.6526003
  • Filename
    6526003