A study on split-output TSPC CMOS circuits

Author

Antaki, Bernard ; Patenaude, Serge ; Trognon, Laure ; Savaria, Yvon

Author_Institution

Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada

Volume

3

fYear

1997

fDate

9-12 Jun 1997

Firstpage

1892

Abstract

In this paper, we present a heuristic study of a class of CMOS true single-phase clocked circuits (TSPC). TSPC circuits have proven to yield good performances at high frequencies. The proposed method may speed up design by identifying technology insensitive circuit properties. Our study focuses on split-output circuits which are believed to yield better performances than the other single-phase clocked circuits. We also present a characterization of the performances of these circuits as a function of load with NORTEL 0.8 μm CMOS technology. With realistic (nonideal) Hspice simulated netlist extracted from layout, we observed that the maximum operating frequency for split-output was 1.17 GHz. It is shown that the maximum speed of TSPC latches obtained with our simple suboptimal design method does not directly decrease with loading as in static gates. Finally, the speed degradation of the studied circuit with degraded clocks is characterized

Keywords

CMOS logic circuits; integrated circuit design; logic design; timing; 0.8 micron; 1.17 GHz; Hspice simulated netlist extraction; NORTEL CMOS technology; TSPC CMOS circuits; TSPC latches; degraded clocks; performance characterization; speed degradation; split-output circuits; suboptimal design method; technology insensitive circuit properties; true single-phase clocked circuits; CMOS technology; Circuit simulation; Circuit stability; Circuit testing; Clocks; Degradation; Frequency; Latches; Libraries; Proposals;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.621519

Filename

621519