A new true-single-phase-clocked double-edge-triggered flip-flop for low-power VLSI designs

Author

Wang, Jinn-Shyan

Author_Institution

Inst. of Electr. Eng., Nat. Chung-Cheng Univ., Taiwan

Volume

3

fYear

1997

fDate

9-12 Jun 1997

Firstpage

1896

Abstract

A new CMOS double-edge-triggered flip-flop (DETFF) utilizing true single phase clocking is proposed as a promising storage element in low-power VLSI designs. Compared to the previously reported DETFF´s, both the total transistor count and the number of clocked transistors per flip-flop are reduced to save the power consumption. A clock system is defined in this paper to include a clock generator, clock distribution networks, and clocked flip-flops. Different amounts of power consumption of the different clocking system with different edge-triggered flip-flops are analyzed and compared. It is found that this newly proposed DETFF requires less power in every respect. For example, using the proposed DETFF can save up to 36% of power consumption in the clocking system for a pipelined FIR macro

Keywords

CMOS digital integrated circuits; VLSI; flip-flops; integrated circuit design; logic design; timing; 0.6 micron; 1 GHz; CMOS flip-flop; clock distribution networks; clock generator; double-edge-triggered flip-flop; low-power VLSI designs; power consumption reduction; storage element; true-single-phase-clocked flip-flop; Application specific integrated circuits; Clocks; Energy consumption; Finite impulse response filter; Flip-flops; Frequency; Parasitic capacitance; Power generation; Very large scale integration; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.621520

Filename

621520