Simulated performance of 1000BASE-T receiver with different analog front end designs

This paper presents simulation results comparing different analog front end (AFE) architectures for Gigabit Ethernet 1000BASE-T receiver design. The objective is to reduce the overall power and area of the receiver by performing partial echo cancellation or equalization in the analog domain. The results indicate that using the best of these architectures can reduce both the resolution of the analog-to-digital converter and the length of the digital filters without sacrificing performance. When the additional complexity of the AFE is considered, the end result is a net reduction in power and area.