A true single-phase clocking scheme for low-power and high-speed VLSI

Author

Kong, Bai-Sun ; Jun, Young-Hyun ; Lee, Kwyro

Author_Institution

LG Semicon Corp., Seoul, South Korea

Volume

3

fYear

1997

fDate

9-12 Jun 1997

Firstpage

1904

Abstract

This paper describes a true-single-phase clocking scheme with charge-recycling differential logic (CRDL). The original CRDL circuit is modified for use with only a single-phase clock signal which is never inverted. This circuit achieves low-power and high-speed operation by eliminating the need for slow PMOS-logic blocks in a pipelined configuration, in addition to using charge-recycling technique. XOR/XNOR gates and a pipelined 32-bit adder are constructed with this circuit technique. The simulation results show that the proposed clocking scheme improves power-delay product by 30.1 to 49.8% as compared to the true-single-phase clocking scheme with conventional differential cascode voltage switch (DCVS) logic

Keywords

MOS logic circuits; adders; clocks; logic CAD; logic gates; pipeline processing; 32 bit; XOR/XNOR gates; charge-recycling differential logic; high-speed VLSI; low-power VLSI; pipelined adder; power-delay product; single-phase clocking scheme; Acceleration; Clocks; Costs; Logic circuits; MOS devices; MOSFETs; Pipelines; Switches; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.621522

Filename

621522