DocumentCode :
2301224
Title :
Parallel clustering algorithms on a reconfigurable array of processors with wider bus networks
Author :
Tsai, Horng-Ren ; Horng, Shi-Jinn ; Tsai, Shun-Shan ; Lee, Shung-Shing ; Kao, Tzong-Wann ; Chen, Chia-Ho
Author_Institution :
Dept. of Inf. Manage., Overseas Chinese of Commerce, Taiwan, China
fYear :
1997
fDate :
10-13 Dec 1997
Firstpage :
630
Lastpage :
637
Abstract :
Clustering techniques are usually used in pattern recognition, image segmentation and object detection. For N patterns and k centers each with M features, in this paper, we first design an O(kM) time optimal parallel algorithm for one pass process of clustering with the k-means method on a linear array of processors with a wider bus network using N1+1c/ processors with one bus network, where c is any constant and c⩾1. Then, based on the proposed algorithm, two O(k) and O(1) time optimal parallel clustering algorithms are also derived using MN1+1c/ and kMN1+1c/ processors with M row and MN row bus networks, respectively. These results improve the best known bounds and achieve cost optimal in their time and processor complexities
Keywords :
image segmentation; object detection; parallel algorithms; pattern recognition; reconfigurable architectures; O(kM) time optimal parallel algorithm; image segmentation; object detection; parallel clustering algorithms; pattern recognition; processor complexity; reconfigurable array of processors; time complexity; wider bus networks; Algorithm design and analysis; Business; Clustering algorithms; Computer architecture; Hypercubes; Image segmentation; Parallel algorithms; Pattern analysis; Pattern recognition; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Systems, 1997. Proceedings., 1997 International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-8186-8227-2
Type :
conf
DOI :
10.1109/ICPADS.1997.652609
Filename :
652609
Link To Document :
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