Accelerated carry-skip adders with low hardware cost

Carry-skip adders have traditionally found favour as a low hardware cost option for implementing addition. This is because w-bit carry-skip adders partitioned into k /spl ap/ /spl radic/w blocks require only an extra k AND gates and k 2-way multiplexers (roughly equivalent to k/2 full adders) relative to ripple-carry adders. However, their delay performance lags that of many other adder structures. For example, carry lookahead adders have a superior time complexity but use much more hardware, equivalent to at least w extra full adders. This paper describes a simple modification to the carry-skip adder structure that reduces its propagation delay by 13-19% for an extra k full adders and k 2-way multiplexers.