A bipolar-PMOS merged basic cell for 0.8 μm BiCMOS sea-of-gates

Author

Hanibuchi, Toshiaki ; Ueda, Masahiro ; Higashitani, Keiichi ; Hatanaka, Masahiro ; Mashiko, Koichiro

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1990

fDate

13-16 May 1990

Abstract

To improve the density of BiCMOS sea-of-gates, bipolar and PMOS transistors are merged to form compact basic cells combined with the gate isolation technique. This structure occupies only 12% of the conventional bipolar transistor area. The density of the basic cell increases by 60% compared with conventional cells. The pull-up BiCMOS circuit achieves the fastest gate delay of 200 ps. A 16-bit multiplier in the test chip fabricated with 0.8 μm BiCMOS technology operates at 18 ns delay time

Keywords

BIMOS integrated circuits; application specific integrated circuits; cellular arrays; logic arrays; 0.8 micron; 16-bit multiplier; 18 ns; 200 ps; ASIC; BiCMOS sea-of-gates; PMOS transistors; SOG; bipolar transistor; bipolar-PMOS merged basic cell; gate array; gate delay; gate isolation technique; logic IC; pull-up BiCMOS circuit; BiCMOS integrated circuits; Bipolar transistors; Circuit testing; Delay; Laboratories; Large scale integration; MOSFETs; Macrocell networks; Research and development; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124657

Filename

124657

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2301641