DocumentCode :
2301739
Title :
System Level Performance Assessment of SOC Processors with SystemC
Author :
Talarico, Claudio ; Koh, Min-Sung ; Rodriguez-Marek, Esteban
Author_Institution :
Sch. of Comput. & Eng. Sci., Eastern Washington Univ., Cheney, WA
fYear :
2007
fDate :
26-29 March 2007
Firstpage :
523
Lastpage :
530
Abstract :
This paper presents a system level methodology for modeling, and analyzing the performance of system-on-chip (SOC) processors. The solution adopted focuses on minimizing assessment time by modeling processors behavior only in terms of the performance metrics of interest. Formally, the desired behavior is captured through a C/C++ executable model, which uses finite state machines (FSM) as the underlying model of computation (MOC). To illustrate and validate our methodology we applied it to the design of a 16-bit reduced instruction set (RISC) processor. The performance metrics used to assess the quality of the design considered are power consumption and execution time. However, the methodology can be extended to any performance metric. The results obtained demonstrate the robustness of the proposed method both in terms of assessment time and accuracy
Keywords :
microprocessor chips; performance evaluation; reduced instruction set computing; system-on-chip; 16 bit; 16-bit reduced instruction set processor; C/C++ executable model; SystemC; finite state machines; system level performance assessment; system-on-chip processors; Application software; Circuit simulation; Computational modeling; Energy consumption; Hardware; Measurement; Power system modeling; Process design; Switches; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Engineering of Computer-Based Systems, 2007. ECBS '07. 14th Annual IEEE International Conference and Workshops on the
Conference_Location :
Tucson, AZ
Print_ISBN :
0-7695-2772-8
Type :
conf
DOI :
10.1109/ECBS.2007.69
Filename :
4148970
Link To Document :
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