A complex multiplier architecture based on redundant binary arithmetic

A new approach for high-speed complex multiplication and its VLSI architecture is presented. By employing redundant binary (RB) arithmetic, an N-hit complex multiplication is reduced to a pair of N RB partial products (RBPPs) additions. Also, an efficient RB encoding scheme proposed in this paper enables us to generate RBPPs without hardware and delay overheads compared to binary partial product generation. The proposed algorithm results in a parallel architecture that consists of two symmetric tree structures, one is responsible for real part and the other is for imaginary part of final complex product. Its architectural regularity results in a compact layout, and makes it very attractive for VLSI realization. As a test vehicle, an 8-bit complex multiplier core has been designed with 0.8 μm CMOS technology