A complex multiplier architecture based on redundant binary arithmetic

Author

Shin, Kyung-Wook ; Song, Bang-Sup

Author_Institution

Dept. of Electron. Eng., Kumoh Nat. Univ. of Technol., Kumi, South Korea

Volume

3

fYear

1997

fDate

9-12 Jun 1997

Firstpage

1944

Abstract

A new approach for high-speed complex multiplication and its VLSI architecture is presented. By employing redundant binary (RB) arithmetic, an N-hit complex multiplication is reduced to a pair of N RB partial products (RBPPs) additions. Also, an efficient RB encoding scheme proposed in this paper enables us to generate RBPPs without hardware and delay overheads compared to binary partial product generation. The proposed algorithm results in a parallel architecture that consists of two symmetric tree structures, one is responsible for real part and the other is for imaginary part of final complex product. Its architectural regularity results in a compact layout, and makes it very attractive for VLSI realization. As a test vehicle, an 8-bit complex multiplier core has been designed with 0.8 μm CMOS technology

Keywords

CMOS logic circuits; VLSI; encoding; multiplying circuits; parallel architectures; redundant number systems; 0.8 micron; 8 bit; CMOS technology; VLSI architecture; compact layout; complex multiplier architecture; encoding scheme; parallel architecture; partial products additions; redundant binary arithmetic; symmetric tree structures; Arithmetic; CMOS technology; Delay; Encoding; Hardware; Parallel architectures; Testing; Tree data structures; Vehicles; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.621532

Filename

621532