Title :
A suggestion for low-power current-sensing complementary pass-transistor logic interconnection
Author :
Cheng, Kuo-Hsing ; Yee, Liow Yu ; Chen, Jiaii-Hung
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan
Abstract :
In this paper, a new circuit interconnection scheme of the low-power current-sensing complementary pass-transistor logic (LCSCPTL) is proposed and analyzed. The proposed new circuit scheme using full-swing and non-full-swing output signals to control the NMOS pass transistor logic tree network. Due to the non-full-swing outputs and the current-sensing scheme, the new logic circuit scheme can improve the power dissipation and operation speed. The non-full-swing LCSCPTL is applied to the design of the parallel multiplier. The 4-2 compressors and the conditional carry selection scheme are used in this design to achieve regular layout and improve the operation speed. Moreover, the 1.2 V 8×8-bit parallel multiplier can be fabricated without changing the conventional 5 V CMOS process. The operation speed of the parallel multiplier is 32 ns for 1.2 V supply voltage
Keywords :
CMOS logic circuits; VLSI; digital arithmetic; integrated circuit interconnections; logic design; multiplying circuits; 1.2 V; 32 ns; 4-2 compressors; 8 bit; CMOS process; NMOS pass transistor logic tree network; circuit interconnection scheme; complementary pass-transistor logic; conditional carry selection scheme; current-sensing; full-swing output signals; low-power scheme; nonfull-swing output signals; operation speed; parallel multiplier; power dissipation; Compressors; Integrated circuit interconnections; Logic circuits; Logic design; MOS devices; MOSFETs; Power amplifiers; Power dissipation; Transconductance; Voltage;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621533
