DocumentCode :
2302050
Title :
Full QoS Support with 2 VCs for Single-chip Switches
Author :
Martínez, Alejandro ; Alfaro, Francisco J. ; Sánchez, José L. ; Duato, José
Author_Institution :
Escuela Politecnica Superior, Univ. Castilla-La Mancha
fYear :
2006
fDate :
24-26 July 2006
Firstpage :
239
Lastpage :
242
Abstract :
Current interconnection standards providing hardware support for quality of service (QoS) consider up to 16 virtual channels (VCs) for this purpose. However, most implementations do not offer so many because VCs increase the complexity of the switch and the scheduling delays. We have shown that this number of VCs can be significantly reduced, because it is enough to use two VCs for QoS purposes at each switch port. In this paper, we explore two alternative switch designs that take advantage of this reduction
Keywords :
communication complexity; logic design; multiprocessor interconnection networks; network interfaces; network-on-chip; packet switching; quality of service; telecommunication channels; telecommunication traffic; interconnection standard; network interface; quality of service; scheduling delay; single-chip switches; switch complexity; switch design; virtual channel; Delay; Hardware; Job shop scheduling; Network interfaces; Proposals; Quality of service; Silicon; Switches; Telecommunication traffic; Traffic control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Network Computing and Applications, 2006. NCA 2006. Fifth IEEE International Symposium on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7695-2640-3
Type :
conf
DOI :
10.1109/NCA.2006.33
Filename :
1659499
Link To Document :
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