DocumentCode :
2302319
Title :
Combating NBTI Degradation via Gate Sizing
Author :
Yang, Xiangning ; Saluja, Kewal
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI
fYear :
2007
fDate :
26-28 March 2007
Firstpage :
47
Lastpage :
52
Abstract :
NBTI is becoming one of the dominant circuit reliability concerns in nano-scale technologies. We believe that designers can combat NBTI degradation using appropriate circuit constraints. This paper presents a design technique to tolerate NBTI degradation by gate sizing. We provide an NBTI-aware gate sizing problem formulation and propose a solution method. The experimental results for MCNC´91 benchmark circuits show that for NBTI tolerance the purposed method results in less than 1% area increase in most cases while a formulation based on traditional performance focused methods may lead to over 4% area increase
Keywords :
benchmark testing; circuit reliability; nanotechnology; NBTI degradation; circuit reliability; gate sizing; nano scale technologies; negative bias temperature instability; CMOS technology; Degradation; Delay; Digital circuits; MOSFETs; Niobium compounds; Random access memory; Timing; Titanium compounds; Turning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2795-7
Type :
conf
DOI :
10.1109/ISQED.2007.48
Filename :
4149010
Link To Document :
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