Title :
Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI
Author :
Deng, Jie ; Kim, Keunwoo ; Chuang, Ching-Te ; Wong, H. S Philip
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA
Abstract :
We propose selective scaling of device footprint for 65 nm and beyond CMOS technologies. The benefits of selective scaling of device footprint are illustrated using an ultra-thin body (UTB) fully-depleted SOI (FD-SOI) transistor as an example. We study the effect of footprint scaling on device, circuit, and system level performance. A complete 2D device structure is modeled for the numerical analysis. The results predict that an optimal footprint design can provide 30% smaller chip layout area, 20% faster speed and 10% less dynamic power on overall chip performance benchmarked with a 53-bit pipelined multiplier
Keywords :
CMOS integrated circuits; integrated circuit design; silicon-on-insulator; transistors; 2D device structure; 53 bit; 65 nm; CMOS technologies; device footprint scaling; fully-depleted SOI transistor; numerical analysis; pipelined multiplier; CMOS technology; Circuit simulation; FETs; Numerical analysis; Numerical models; Performance gain; Plugs; Power generation; Power system modeling; Semiconductor device modeling;
Conference_Titel :
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2795-7
DOI :
10.1109/ISQED.2007.60
