• DocumentCode
    2302680
  • Title

    A Unified Optimal Voltage Selection Methodology for Low-Power Systems

  • Author

    Dabiri, Foad ; Jafari, Roozbeh ; Nahapetian, Ani ; Sarrafzadeh, Majid

  • Author_Institution
    California Univ., Los Angeles, CA
  • fYear
    2007
  • fDate
    26-28 March 2007
  • Firstpage
    210
  • Lastpage
    218
  • Abstract
    Reduction in power consumption has been an important concern in low-power and high-performance systems. This paper addresses the problem of static voltage scaling in such systems which is a well studied technique. In this paper we present an optimal methodology for static voltage scaling. Previous techniques use path-based timing constraints in the system model which requires exponential runtime even for problem generation. Our main contribution is the unified formulation with linear number of constraints in the optimization problem as opposed to the exponential number. This methodology results in a fully polynomial time solvable problem. Our formulation can be applied to dynamic voltage scaling on single or multiple resources and moreover, it results in a convex optimization problem which can be solved in fully polynomial time. We propose a general formulation for bounded supply voltage assignments as well. Furthermore, we present two heuristics to find and/or map optimal voltages to discrete levels. We evaluated the performance of our techniques on benchmarks from TGFF and MPEG4 video encoder. An average of 43.96% power reduction was gained for unbounded supply voltage assignment along with PS 40% average power saving where discrete voltage levels are available
  • Keywords
    circuit optimisation; convex programming; integrated circuit design; integrated circuit modelling; low-power electronics; bounded supply voltage assignments; convex optimization problem; dynamic voltage scaling; low-power systems; optimal voltage selection methodology; path-based timing constraints; power consumption reduction; static voltage scaling; video encoder; CMOS digital integrated circuits; Constraint optimization; Dynamic voltage scaling; Energy consumption; Polynomials; Power dissipation; Runtime; Threshold voltage; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-7695-2795-7
  • Type

    conf

  • DOI
    10.1109/ISQED.2007.27
  • Filename
    4149036