DocumentCode :
2302825
Title :
A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays
Author :
Drego, Nigel ; Chandrakasan, Anantha ; Boning, Duane
Author_Institution :
Microsystems Technol. Labs., MIT, Cambridge, MA
fYear :
2007
fDate :
26-28 March 2007
Firstpage :
281
Lastpage :
286
Abstract :
A test-structure comprising a dual-slope integrating analog-to-digital converter, auto-zeroing circuitry, digital control logic and a large array of devices under test (DUTs) has been developed to isolate threshold voltage variation. Threshold-voltage (VT) isolation is achieved by testing all DUTs in the subthreshold regime where drain-to-source current is an exponential function of VT. Spice simulations show that the structure is at least an order of magnitude more sensitive to VT variation than to channel length variation. This, in combination with a hierarchical access scheme and leakage control system, allows efficient characterization of DeltaVT for ~70,000 NMOS and ~70,000 PMOS devices in a dense 2mm times 2mm DUT array
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit design; integrated circuit manufacture; auto-zeroing circuitry; devices under test; digital control logic; dual-slope integrating analog-to-digital converter; large MOSFET arrays; threshold-voltage variation; Analog-digital conversion; Circuit testing; Digital control; Logic arrays; Logic circuits; Logic devices; Logic testing; MOS devices; MOSFET circuits; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2795-7
Type :
conf
DOI :
10.1109/ISQED.2007.24
Filename :
4149048
Link To Document :
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