Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage

A single-bit-line (BL) static RAM (SRAM) circuit that employs adiabatic charging of a word line during a read operation was found to provide a large dynamic noise margin (DNM) for reading. Single-BL reading is achieved by using a left access transistor and a shared reading port. The shared reading port greatly reduces the BL capacitance, enabling the voltage of the BL connected to the low-voltage node of the flip-flop to change from the precharge voltage to GND. An analysis of the time-wise change in DNM revealed that the read noise margin of this circuit was 1.9 times larger than that of a conventional two-BL circuit. This circuit enables the design of an SRAM that is smaller than a conventional one, resulting in lower energy consumption.