Title :
14nm FDSOI technology for high speed and energy efficient applications
Author :
Weber, Olivier ; Josse, E. ; Andrieu, F. ; Cros, A. ; Richard, Evelyne ; Perreau, P. ; Baylac, E. ; Degors, N. ; Gallon, C. ; Perrin, Eric ; Chhun, S. ; Petitprez, E. ; Delmedico, S. ; Simon, Jerome ; Druais, G. ; Lasserre, S. ; Mazurier, J. ; Guillot, N.
Author_Institution :
LETI, CEA, Grenoble, France
Abstract :
This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m2 high-density bitcell and two 0.090°m2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.
Keywords :
MOSFET; SRAM chips; oscillators; silicon-on-insulator; FBB; FDSOI technology; Si; drive current; dynamic power reduction; energy efficient applications; forward back bias; full single-port SRAM; gate-to-drain capacitance; high speed applications; high-density bitcell; ring oscillators; size 14 nm; strain-engineered FDSOI transistors; Delays; Energy efficiency; Logic gates; MOS devices; Random access memory; Silicon; Very large scale integration;
Conference_Titel :
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3331-0
DOI :
10.1109/VLSIT.2014.6894343
