• DocumentCode
    2303322
  • Title

    A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances

  • Author

    Kahng, Andrew B. ; Topaloglu, Rasit Onur

  • Author_Institution
    Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA
  • fYear
    2007
  • fDate
    26-28 March 2007
  • Firstpage
    467
  • Lastpage
    474
  • Abstract
    Metal fills, which are used to reduce metal thickness variations due to chemical-mechanical polishing (CMP), increase the capacitances in a circuit. Although current extraction tools are accurate in handling grounded fills and regular interconnects, for floating fills, these tools are based on certain approximations, such as assuming that floating fills are grounded or each fill is merged with neighboring ones. To reduce such inaccuracies, the authors provide a design of experiments (DOE), which will be used in addition to what is available in the extraction tools for regular interconnects. Through the proposed DOE set, a design or mask house can generate normalized fill tables to remove the inaccuracies of the extraction tools in the presence of floating fills. The capacitance values are updated using these normalized fill tables. The proposed DOE enables extensive analyses of the fill impacts on coupling capacitances. The authors show through extensive 3D field solver simulations that the assumptions used in extractors result in significant inaccuracies. The authors present analyses of fill impacts for an example technology, and also provide analyses using the normalized fill tables to be used in the extraction flow for three different standard fill algorithms
  • Keywords
    chemical mechanical polishing; design of experiments; integrated circuit interconnections; integrated circuit layout; 3D field solver simulations; chemical-mechanical polishing; design of experiments; fill impacts; floating fills; mask house; metal fills; Algorithm design and analysis; Capacitance; Chemical engineering; Computer science; Data mining; Equations; Foundries; Integrated circuit interconnections; Pattern analysis; US Department of Energy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-7695-2795-7
  • Type

    conf

  • DOI
    10.1109/ISQED.2007.11
  • Filename
    4149079