DocumentCode :
2303370
Title :
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization
Author :
Chang, Kai-Hui ; Papa, David A. ; Markov, Igor L. ; Bertacco, Valeria
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI
fYear :
2007
fDate :
26-28 March 2007
Firstpage :
487
Lastpage :
494
Abstract :
Dramatic increases in design complexity and advances in IC manufacturing technology affect all aspects of circuit performance and functional correctness. As interconnect increasingly dominates delay and power at the latest technology nodes, much effort is invested in physical synthesis optimizations, posing great challenges in validating the correctness of such optimizations. Common design methodology delays the verification of physical synthesis transformations until the completion of the design phase. However, this approach is not sustainable because the isolation of potential errors becomes extremely challenging in current complex design efforts. In addition, the lack of interoperability between verification and debugging tools greatly limits engineers´ productivity. Since the design´s functional correctness should not be compromised, considerable resources are dedicated to checking an ensuring correctness at the expense of improving other aspects of design quality. To address these challenges, the paper proposed a fast incremental verification system for physical synthesis optimizations, InVerS, which includes capabilities for error detection, diagnosis, and visualization. This system helps engineers to discover errors earlier, simplifies error isolation and correction, thus reducing verification effort and enabling more aggressive optimizations to improve performance
Keywords :
error detection; integrated circuit manufacture; open systems; optimisation; program debugging; program verification; InVerS; circuit similarity metrics; debugging tools; design methodology delays; error detection; error diagnosis; error visualization; incremental verification system; integrated circuit manufacturing technology; interoperability; physical synthesis optimizations; Circuit optimization; Circuit synthesis; Delay; Design methodology; Error correction; Integrated circuit interconnections; Isolation technology; Manufacturing; Power system interconnection; Visualization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2795-7
Type :
conf
DOI :
10.1109/ISQED.2007.94
Filename :
4149082
Link To Document :
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