Anti-fuse memory array embedded in 14nm FinFET CMOS with novel selector-less bit-cell featuring self-rectifying characteristics

Author

Liu, Yanbing ; Chi, M.H. ; Mittal, Anish ; Aluri, G. ; Uppal, S. ; Paliwoda, P. ; Banghart, E. ; Korablev, K. ; Liu, B. ; Nam, Minho ; Eller, M. ; Samavedam, S.

Author_Institution

GlobalFoundries, Malta, NY, USA

fYear

2014

fDate

9-12 June 2014

Firstpage

1

Lastpage

2

Abstract

A novel anti-fuse memory array is presented in this paper featuring one-capacitor (1C) per bit-cell design and fully compatible with 14nm FinFET CMOS technology. The rectifying I-V characteristics of the metal-insulator-semiconductor (MIS) structure after programming prevents the sneak current in the cross-point array, therefore no need for select transistor in each cell. Thus enables the smallest reported bit-cell with area measuring 0.036 μm².

Keywords

CMOS memory circuits; MIS structures; MOSFET; FinFET CMOS technology; I-V characteristics; MIS structure; anti-fuse memory array; cross-point array; metal-insulator-semiconductor structure; one-capacitor per bit-cell design; selector-less bit-cell; self-rectifying characteristics; size 0.036 mum; size 14 nm; Arrays; Dielectrics; FinFETs; Logic gates; Programming; Resistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4799-3331-0

Type

conf

DOI

10.1109/VLSIT.2014.6894356

Filename

6894356