Fast successive-approximation A/D converters

A novel successive-approximation analog-to-digital converter is described. It combines a string of equal-valued polysilicon resistors and a set of ratioed capacitors in a unique circuit configuration so that high-speed operation can be achieved. The comparator is realized by a chopper-stabilized amplifier to reduce the effect of the offset voltages of MOS amplifiers. The converter performs an 8-b monotonic conversion with a differential nonlinearity less than 1 LSB in 0.77 μs, which is exceedingly fast for a CMOS successive-approximation A/D converter. The die area is 3750 mil². This new conversion technique can also be utilized in a pipelined A/D converter and enables it to achieve high speed. An extension of the technique to 10 b implemented in a 2-μm double-poly CMOS process achieved 1.5 MSample/s conversion rate. The 10-b converter occupied 2600 mil²