Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design

In this paper, we introduce a new, highly accurate, package parasitics estimation technique (PME: package model estimator) that can simultaneously consider both on-chip and off-chip parasitic effects at the early stage of chip design. The performance of the proposed technique was verified by application to a substrate package designed for mass production. This paper mainly focuses on the estimation of electrical models of unrouted PCB traces in the early stage of package design by the use of the weighting factor (W) reflecting the irregular routability of a substrate design. It is clearly shown that the proposed estimation algorithm produces excellent results compared to the post-simulation models for simple as well as complicated package designs. The efficient chip-package co-design technique, which accounts for all necessary parasitic effects of the package, can accurately predict the upper and lower boundaries of the noise margin for worst cases