Automatic synthesis of modular data conversion architectures and functional building blocks

An open, vertically integrated CAD environment is described for automatic synthesis of data conversion systems covering a wide range of conversion specifications. A set of key functional building blocks has been devised for synthesising charge redistribution, successive approximation, flash, two-step flash, subranging, and pipeline conversion architectures. Functional models are included for architecture performance verification, including statistical information concerning non-linearity characteristics, and thereafter defining the required specifications for the lower level components. These, in turn, are synthesised using rule-driven topology selection with prioritized specifications for more flexible knowledge build-up. An example is given of the synthesis of a two-step flash ADC envisaged for high-speed applications