Design of CMOS A/D converters with folding and/or interpolating techniques

For resolutions around 8 bit the flash A/D converter is the fastest possible architecture. The sampling speed of the flash converter is limited to the maximum speed of a comparator in that technology. All other A/D converter architectures, such as two step, pipelined, etc., have a comparator as a building block, so the sampling speed of these converters is maximum that of the flash converter based on the same comparator. On the other hand, the major disadvantage of the flash converter is the 2ⁿ dependency of several parameters as power consumption, area, and input capacitance. Several A/D architectures have been proposed that try to keep the same high sampling speed of the flash converter and avoid some of the disadvantages. These architectures are based on the analog pre-processing of the input signal before converting it into a digital signal. In bipolar technology, several high speed A/D converters have been published based on an analog preprocessing architecture using the folding and interpolation principle. In CMOS technology only the interpolation technique has been reported. In this paper, the interpolation and folding analog preprocessing techniques are discussed in CMOS technologies