DocumentCode
2303839
Title
Defect or Variation? Characterizing Standard Cell Behavior at 90nm and below
Author
Aitken, Robert
Author_Institution
ARM R&D, Sunnyvale, CA
fYear
2007
fDate
26-28 March 2007
Firstpage
693
Lastpage
698
Abstract
Historically, design margin and defects have been viewed as different topics, one part of design and the other part of test. Shrinking process geometries are making the two part of a continuum. This paper discusses the leakage and delay behavior associated with classic resistive defects and compares it with transistor variation due to lithography
Keywords
fault diagnosis; integrated circuit testing; lithography; delay behavior; leakage behavior; lithography; resistive defects; shrinking process geometries; standard cell behavior; transistor variation; Circuit faults; Circuit testing; Computational geometry; Delay effects; Design for testability; Libraries; Manufacturing; Research and development; Stress; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
0-7695-2795-7
Type
conf
DOI
10.1109/ISQED.2007.54
Filename
4149115
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