A first-order current-steering sigma-delta modulator

Author

Comino, Vittorio ; Steyaer, Michael ; Temes, Gabor

Author_Institution

California Univ., Los Angeles, CA, USA

fYear

1990

fDate

13-16 May 1990

Abstract

A novel architecture for a first-order sigma-delta modulator is presented. The system can operate at a high sampling frequency, can be used as a building block for higher-order modulators, and uses circuit techniques that are largely technology-independent. The system was realized in a 2-μm n-well double-metal single-poly CMOS technology. The integrated modulator circuit works accurately with a maximum sampling frequency of 30 MHz. A sampling frequency of 18.5 MHz gives the best results in terms of signal-to-noise ratio (SNR). The oversampling ratio is 128. The Nyquist frequency is 144 kHz and the baseband limit is 72 kHz. The corresponding theoretical SNR is 63 dB, or equivalent to a resolution of 10.5 b

Keywords

CMOS integrated circuits; data conversion; delta modulation; modulators; 144 kHz; 18.5 MHz; 2 micron; 30 MHz; 63 dB; 72 kHz; Nyquist frequency; SNR; baseband limit; building block; current-steering; data convertors; double-metal; first-order; high sampling frequency; higher-order modulators; integrated modulator circuit; monolithic IC; n-well; oversampling ratio; sigma-delta modulator; single-poly CMOS technology; CMOS technology; Clocks; Delta-sigma modulation; Frequency; Latches; Operational amplifiers; Sampling methods; Signal resolution; Switches; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124672

Filename

124672