A VLSI decimation filter for sigma-delta A/D converters

This paper describes a VLSI based on polyphase recursive allpass filter structures. The proposed architecture is found to be flexible, efficient and requires either comparable or less register and arithmetic resources than other architectures. Both the multirate decimation filter structure and the architecture proposed are very different from the popular architectures based on comb filters. It is believed that the flexibility of the architecture would make it attractive as a standard module in an ASIC library for a variety of applications that require oversampled A/D converters