Small-Delay Defect Detection in the Presence of Process Variations

Interconnect based defects such as resistive via are becoming more prevalent in nanoscale designs. Such defects can be classified as latent defects that affect circuit reliability and are generally modeled as small-delay defects. One method to detect these defects is to estimate the slack interval of the path being tested. In the presence of process variations, however, it is difficult to determine if the deviation in circuit delay is due to random process parameters or due to the presence of a latent defect. In this paper we analyze resistive interconnect defects (in this context) and suggest a test approach that increases the probability of detection of small-delay defects that can otherwise escape detection due to the uncertainty caused by process variations