Title :
Enhanced Identification of Strong Robustly Testable Paths
Author :
Flanigan, Edward ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ. at Carbondale, IL
Abstract :
Strong robustly sensitizable paths play an essential role in determining circuit timing characteristics as well as defining delay fault diagnosis resolution. A novel technique is presented that increases the number of strong robustly sensitizable path delay faults (PDFs) through validation. Experimental results show that the proposed strong robust validation technique significantly improves the number of strong robustly sensitizable PDFs therefore increases diagnosis resolution and improves the ability to correctly determine circuit timing characteristics
Keywords :
fault diagnosis; integrated circuit testing; timing; circuit timing characteristics; delay fault diagnosis resolution; strong robust validation technique; strong robustly sensitizable path delay faults; strong robustly testable paths; Automatic testing; Circuit faults; Circuit testing; Delay; Electronic equipment testing; Equations; Fault diagnosis; Performance evaluation; Robustness; Timing;
Conference_Titel :
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2795-7
DOI :
10.1109/ISQED.2007.73
