Title :
Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications
Author :
Jong Kyung Park ; Seung-Yoon Kim ; Ki-Hong Lee ; Seung Ho Pyi ; Seok-Hee Lee ; Byung Jin Cho
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
Abstract :
An ultrathin junctionless (JL) charge trap flash (CTF) thin-film transistor (TFT) with a sub-2 nm thick poly-Si channel is demonstrated for 3D stacked flash memory. It provides the excellent memory performance of faster program/erase (P/E) speed, larger memory window (>12 V), and better endurance (>104 cycles) than inversion-mode (IM) devices; this device also has excellent 10-year data retention at 150 °C, as well as improved on/off current ratio (>108) and subthreshold swing (SS). The transfer characteristics and the memory performance as a function of the poly-Si channel thickness (TCh) are also systematically investigated.
Keywords :
NAND circuits; elemental semiconductors; flash memories; silicon; thin film transistors; three-dimensional integrated circuits; 3D stacked flash memory; Si; inversion-mode devices; memory performance; memory window; poly-Si channel thickness; program-erase speed; size 2 nm; subthreshold swing; temperature 150 C; transfer characteristics; ultrathin junctionless CTF TFT; ultrathin junctionless charge trap flash thin-film transistor; Electric fields; Hafnium; Logic gates; Oxidation; Performance evaluation; Silicon; Three-dimensional displays;
Conference_Titel :
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3331-0
DOI :
10.1109/VLSIT.2014.6894385