Title :
15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process
Author :
Mitard, J. ; Witters, L. ; Loo, Roger ; Lee, S.H. ; Sun, J.W. ; Franco, Jacopo ; Ragnarsson, Lars-Ake ; Brand, A. ; Lu, Xinyi ; Yoshida, Norihiro ; Eneman, Geert ; Brunco, D.P. ; Vorderwestner, M. ; Storck, Pascal ; Milenin, A.P. ; Hikavyy, Andriy ; Waldr
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CETINV-normalized GM,SAT,INT of 6.7 nm.mS/μm, the Si0.3Ge0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.
Keywords :
Ge-Si alloys; MOSFET; germanium; isolation technology; quantum well devices; SRB; STI-last integration scheme; SiGe; fin replacement process; high-performance low-defectivity strained-germanium pFinFET; quantum well pFinFET; shallow trench isolation; size 15 nm; size 35 nm; strain relaxed buffers; Doping; FinFETs; Logic gates; Performance evaluation; Silicon; Silicon germanium; Strain;
Conference_Titel :
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3331-0
DOI :
10.1109/VLSIT.2014.6894391
