Lowest variability SOI FinFETs having multiple Vt by back-biasing

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (V_t) necessary for multiple V_t solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (I_on) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of V_t (A_Vt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (G_m). Back-biasing through the SOTB provides excellent V_t controllability keeping the low V_t variability in contrast to V_t tuning by fin channel doping.