Title :
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Author :
Mondal, Mosin ; Ragheb, Tamer ; Wu, Xiang ; Aziz, Adnan ; Massoud, Yehia
Author_Institution :
Rice Univ., Houston, TX
Abstract :
A network-on-chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected through programmable crosspoints. Since an NoC may provide a number of paths between a given source and destination, manufacturing or runtime faults on one interconnect does not necessarily render the chip useless. It is partly because of this fault tolerance that NoCs have emerged as a viable alternative for implementing communication between functional units of a chip in the nanometer regime, where high defect rates are prevalent. In this paper, the authors quantify the fault tolerance offered by an NoC against process variations. Specifically, the authors develop an analytical model for the probability of failure in buffered global NoC links due to interconnect dishing, and effective channel length variation. Using the developed probability model, the authors study the impact of link failure on the number of cycles required to establish communications in NoC applications
Keywords :
delay circuits; fault tolerance; integrated circuit interconnections; network-on-chip; buffered RC interconnect delay variations; fault tolerance; multicore environment; network-on-chip; on-chip networks; point-to-point interconnects; probability model; Analytical models; CMOS technology; Circuit faults; Delay; Fault tolerance; Hardware; Integrated circuit interconnections; Network-on-a-chip; Planarization; Surface resistance;
Conference_Titel :
Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-2795-7
DOI :
10.1109/ISQED.2007.129