A TMR Scheme for SEU Mitigation in Scan Flip-Flops

Radiation from outer space comprising of charged particles can affect transistors in integrated circuits resulting in a change in the state of transistors. This creates a temporary transient effect that corrupts logic within a circuit, and hence it is called a single event upset (SEU). The SEU if captured may lead to soft error. With the progress of microelectronic technology, the shrinkage of transistor sizes is enabling the integration of more transistors in a circuit, making them more vulnerable to soft errors. Any future attempt toward scaling will have to address the problems of circuit reliability which is affected by the increasing number of failures arising from soft errors. In this paper the authors present a novel register design which can detect and correct soft errors. The authors add a redundant latch to the existing structure of a flip-flop and functional data is simultaneously registered at multiple latches. The content of these multiple latches are fed to a majority voter, and if the content of any of these latches is corrupted by a soft error, it is filtered out through the majority voting circuit. This design provides tolerance over the entire vulnerability region of a flip-flop unlike other published solutions. This design can be operated as a simple scan flip-flop or scan hold flip-flop and thus is useful for system testability purposes. The detection and correction operation takes place concurrently, with 23% degradation in system performance